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The 2.5V banks are all fully used
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I vaguely recall that the receiver inputs are powered from VCCPD and in many cases LVDS can be received on any clock pin (don't hold me to that ...). The clock inputs will not have a SERDES block, but you could investigate whether a clock pin and fabric SERDES is a work-around for the couple of signals you need.
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The LVDS streams have embedded clocks with a guaranteed transition every 12 clocks.
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Did you try an AC-coupled link? (Your comments above imply you only tested DC-coupled links, with a modified Vcm)
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Any thoughts?
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I'll have a think about it some more.
I can think of one way that would work. 800Mbps is slow compared to transceiver rates. Since transceivers come in pairs, and you only want the RX, you could use the TX and an external high-speed XOR gate. The inputs to the XOR gate would be your signal and the transceiver TX. The XOR output would be AC-coupled to the receiver. The TX would output a PRBS pattern at say 4x the data rate (3.2Gbps). The output of the XOR is then modulated, allowing the RX signal to use the clock-and-data recovery (CDR) lock-to-data mode. The receive logic would then XOR the receiver output with the PRBS signal (appropriately delayed). The result will be a 4x over-sampled version of your receive signal. I'm currently using the XOR modulation technique to AC-couple 5Gbps and 10Gbps signals with a negative common-mode voltage onto an FPGA.
Cheers,
Dave
Honored Contributor
