Honored Contributor
Honored ContributorHi Dave,
Thanks for your very informative response. We cannot use regular LVDS pins for "historic" reasons, it is a small revision of an existing design. The 2.5V banks are all fully used. In fact, we need 6 channels in total, 4 are realized with regular LVDS pins and 2 by transceivers. The LVDS streams have embedded clocks with a guaranteed transition every 12 clocks. The further explain: The design is already working. We did originally connect the LVDS signal directly to the transceiver inputs, however we had quite some problems with transmission errors. Then we got aware of this small footnote "LVDS only supported with 0.82 Vcm" and pulled down the Vcm by adding 1.3kOhm resistors to both lines of the pair as a hot-fix. This pulled the Vcm down to about 0.82V with our typical transmitter. This improved the link stability a lot. However we have sometimes still intermittent problems with errors (very random, even the same system sometimes show no problems for hours, then on the next day it produces a lot of errors, cause unclear, just a few suspects...). So we want to solve this Vcm thing in a cleaner way. We also want to improve the clock network as the second concern we have is that the problems are introduced by input clock jitter. But back to the topic: The SN65CML100 you suggested appears to support only termination voltages down to 1.8V. But at Micrel I found the SY54016AR (http://www.micrel.com/_pdf/hbw/sy54016ar.pdf) which looks good as it supports 2.5V/1.8V and 1.2V. But when looking further at the Altera documentation to find out if 1.2V would do instead of 1.5V, I realized that with CML it is assumed that both sides have termination resistors to Vcco (see figure 5a in above mentioned datasheet on page 11) while the transceivers (PCML) terminate to 0.82V. So I think when I connect the SY54016AR (with Vcco of 1.2V) to the FGPA (either with external termination to 1.2V or using the internal termination of the FPGA), I will not achieve this required Vcm of 0.82V +/- 10%. So when thinking about this I think only AC-coupling is supported except for other transceivers outputs (PCML1.5/1.4) or (non-existing?) LVDS outputs with Vcm = 0.82V. In fact this is also what Table 1-2 is saying in http://www.altera.com/literature/hb/cyclone-iv/cyiv-52001.pdf. Hmm, I guess I should not look for a CML output device but for something else differential with a Vcm of 0.82V? Any thoughts? Thanks, Thomas www.entner-electronics.com (Home of EEBlaster)
