Honored Contributor
Honored Contributor1. Why not use the Cyclone IV LVDS receiver SERDES block?
From the handbook: "LVDS interfaces up to 840 Mbps transmitter (Tx), 875 Mbps Rx" 2. Assuming you cannot use an LVDS SERDES ... Since the LVDS common mode is higher than the FPGA common-mode voltage, I suspect you could create a resistive divider that works ... TI have a range of interfacing app notes ... http://www.ti.com.cn/cn/lit/an/scaa062/scaa062.pdf Look at Figure 13, which uses the following 1.5Gbps device http://www.ti.com/product/sn65cml100 I did not check that the Vcm was compatible with the FPGA though. Micrel also has a range of "Any Differential" translators, so you just need to find a CML output with a compatible Vcm. http://www.micrel.com/index.php/en/products/clock-timing/clock-data-distribution/level-translators.html http://www.micrel.com/index.php/en/products/clock-timing/clock-data-distribution/receivers-buffer-drivers.html You understand of course that a transceiver is NOT a replacement for an LVDS receiver right? The clock-and-data recovery (CDR) unit in the transceiver will need to be forced into lock-to-reference mode, since it will not be able to operate in lock-to-data mode, since you do not have enough data transitions. Cheers, Dave
