Cyclone V SoC - Shared Memory Controller

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I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code!

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Hi,

I would really appreciate a copy of your project if you don't mind sharing to get more experience with the FPGA-HPS bridges.

nalkhateeb@teamist.com

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I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code!

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This is exactly what I'm trying to do, but I have not been able to get it working. It would be great to see a good example - I'm unable to PM you so can you send it to me at cmjcampbell@gmail.com? Thank you!

I am also interested in looking through an example project. I've been struggling with the FPGA-to-HPS SDRAM interface for a few weeks and haven't gotten anywhere.

WH2011, would you be able to post your example project publicly?

Hi , could you share your example please. My mail is mecatronicman@hotmail.com

Thanks

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I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code!

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Hi,

If you still have it, I would really appreciate a copy of the project and the source code. My email is dylanchippy@gmail.com

Thanks a lot

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I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code!

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Hi WH2011,

I would greatly appreciate a copy of your project. Could you email it to "felixw256 _at_ gmail _dot_ com"?

Many thanks,

Felix

I'm trying to get the FPGA to HPS SDRAM interface working but it just freezes on memory access. I have set up a Avalon-MM Read/Write port on a DE0-nano-SoC. I have tried reading or writing to a lot of different addresses but the result remains the same.

* What address are you using? I have done most of the testing with 0x30000000 which should hit the ram regardless of the 0x20000000 offset described in this thread.

* Have you seen any examples of this that is compatible with DE0-nano SoC?

* Is it enough to build the preloader? I built the preloader from my fpga project but then I imported another U-boot because my preloader would not work with U-boot from the SD image. I also had to replace the kernel, so a lot of the hardware fails to initialize. So far I believe that this should be ok for testing as long as the SDRAM controller gets initialized by the preloader. I can see that the reset bits for the FPGA to SDRAM ports gets set when I use this setup.

* Is there any way to catch this error in a more controlled way than freezing?

* In case I need to create a bare minimum fpga project to test this, what example should I use as a base?

I have a deep understanding of the FPGA part but my linux skills are still at a very basic level.