Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCyclone V SoC - Shared Memory Controller
Hi @all, I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. ...
Altera_ForumHonored Contributor
Honored ContributorThis design was recently ported to the Cyclone V development kit which you might find useful: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html
