Cyclone V SoC - Shared Memory Controller

I'm trying to get the FPGA to HPS SDRAM interface working but it just freezes on memory access. I have set up a Avalon-MM Read/Write port on a DE0-nano-SoC. I have tried reading or writing to a lot of different addresses but the result remains the same.

* What address are you using? I have done most of the testing with 0x30000000 which should hit the ram regardless of the 0x20000000 offset described in this thread.

* Have you seen any examples of this that is compatible with DE0-nano SoC?

* Is it enough to build the preloader? I built the preloader from my fpga project but then I imported another U-boot because my preloader would not work with U-boot from the SD image. I also had to replace the kernel, so a lot of the hardware fails to initialize. So far I believe that this should be ok for testing as long as the SDRAM controller gets initialized by the preloader. I can see that the reset bits for the FPGA to SDRAM ports gets set when I use this setup.

* Is there any way to catch this error in a more controlled way than freezing?

* In case I need to create a bare minimum fpga project to test this, what example should I use as a base?

I have a deep understanding of the FPGA part but my linux skills are still at a very basic level.