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Altera_Forum's avatar
Altera_Forum
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12 years ago

Cyclone V SoC - Shared Memory Controller

Hi @all, I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code!

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This is exactly what I'm trying to do, but I have not been able to get it working. It would be great to see a good example - I'm unable to PM you so can you send it to me at cmjcampbell@gmail.com? Thank you!