CYCLONE V HPS JTAG Boundary Scan - DDR RAM

Question

Hello,I want to perform JTAG boundary scan on CYCLONE V (5CSEBA2U23I7SN).There is DDR3 RAM (MT41K64M16TW-107) on the board, connected to the HPS (Hard Processor System) side.How can I perform DDR3 RAM testing via the JTAG port of the HPS (Hard Processor System)?For example, I can access the SPI flash (connected to the HPS side) integrated on the board via JTAG using the following command."quartus_hps.exe -c1 -o S"Is there a similar script for DDR RAM?Thanks,

tehjingy_altera · Answer

Hi ieeeHuseyinI believe the tool you are looking for is the System Console.You could read or write the memory address using the tool.Please refer to the links below:https://www.intel.com/content/www/us/en/docs/programmable/683819/21-3/introduction-to-system-console.htmlhttps://www.intel.com/content/www/us/en/programmable/customertraining/webex/Adv_Qsys_SysCon_p2/System_Console.pdfRegardsJingyang, Teh

hsyn · Answer

Thanks for your help. I will examine the documentation for the system console.

Well, it is mentioned in the link I provided below that DDR RAM can be controlled via JTAG boundary scan. Do I need to use an IP core to do this, or can it be done with bit-banging?

https://www.asset-intertech.com/wp-content/uploads/2020/09/testing-ddr3-memory-boundary-scan-jtag.pdf

tehjingy_altera · Answer

HiFor the system console usage you would need to add in an soft IP to bridge the connection.The soft IP required is the jtag-to-host soft IP.Please refer to link below for more info for the soft IP.https://www.intel.com/content/www/us/en/docs/programmable/683130/22-1/spi-agent-jtag-to-host-bridge-cores-48170.htmlRegardsJingyang, Teh

tehjingy_altera · Answer

Hi Any update on this case?Do you have any more question regarding this case?RegardsJingyang, Teh

hsyn · Answer

Hi,Well, is there any way to use the SDRAM Controller Subsystem via the JTAG interface without using the system console?In the link I provided below, I am talking about SDRAM control with openocd.Is it possible to achieve such control?Thanks.https://community.arm.com/support-forums/f/architectures-and-processors-forum/54872/cyclone-v---hps---ddr-ram-control-over-jtag-with-openocd

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CYCLONE V HPS JTAG Boundary Scan - DDR RAM

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