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hsyn's avatar
hsyn
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2 years ago

CYCLONE V HPS JTAG Boundary Scan - DDR RAM

Hello, I want to perform JTAG boundary scan on CYCLONE V (5CSEBA2U23I7SN). There is DDR3 RAM (MT41K64M16TW-107) on the board, connected to the HPS (Hard Processor System) side. How can I perform D...
Board Debug
Configuration
Fpga Devkit
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi


Any update on this case?

Do you have any more question regarding this case?


Regards

Jingyang, Teh


  • hsyn's avatar
    hsyn
    Icon for New Contributor rankNew Contributor
    2 years ago

    I conducted some experiments as shown below.

    However, I couldn't access the SDRAM controller subsystem completely.

    Which registers do I need to configure to access the SDRAM controller subsystem via JTAG?
    Is there a register list available for this purpose?

    All registers are available in the link below.

    However, which registers do I need to configure?

    https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html

    openocd sdram control

    Thanks.