CYCLONE V HPS JTAG Boundary Scan - DDR RAM

I conducted some experiments as shown below.

However, I couldn't access the SDRAM controller subsystem completely.

Which registers do I need to configure to access the SDRAM controller subsystem via JTAG?
Is there a register list available for this purpose?

All registers are available in the link below.

However, which registers do I need to configure?

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html

openocd sdram control

Thanks.