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hsyn's avatar
hsyn
Icon for New Contributor rankNew Contributor
2 years ago

CYCLONE V HPS JTAG Boundary Scan - DDR RAM

Hello, I want to perform JTAG boundary scan on CYCLONE V (5CSEBA2U23I7SN). There is DDR3 RAM (MT41K64M16TW-107) on the board, connected to the HPS (Hard Processor System) side. How can I perform D...
Board Debug
Configuration
Fpga Devkit
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi


There is no ready configuration by Intel on the openocd ram control tool that you are using.

However it is possible the JTAG connection is the Cyclone V JTAG supports the IEE1149.1 standard.

You would need to add the JTAG UART Core IP on your design. Then through the IP you could access the SDRAM.


Regards

Jingyang, Teh