New ContributorMy project for FPGA Cyclone V 5CEFA9F23I7N performs some calculations in between two consecutive IQ samples incoming at frequency 20MHz. In order to have time to calculate everything, I have to set the operating clock close to 500 MHz. Is it possible to set this clock in the FPGA? What is the maximum frequency can I set for this device?
Super ContributorYou can check the Fmax Summary report in the timing analysis. The Fmax Summary reports the maximum frequency of each clock in your design.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
New ContributorThank you but I think your answer is not what I wanted to know. I'm interested in maximum capabilities of the FPGA. What I managed to find out when I use megawizard for Altera PLL IP core it allows to set input reference PLL clock in the range from 5 to 700 MHz and output PLL clock up to 1600 MHz. I think it`s the answer for my question.
Super ContributorHello,
did you already look to the datasheet. Under switching characteristics, there's a core performance chapter. Besides maximum core clock, I would particularly refer to DSP and memory block specs. Even if a core clock of e.g. 500 MHz is feasible, you can't operate DSP or memory blocks at this clock rate.
Second point is to find useful clock speed versus logic complexity tradeoff for your design. Length of combinational path between registers defines the maximal clock speed. Pipelining can help to increase speed by dividing logical and arithmetic operations in multiple steps, utilizing additional registers and increasing latency. For Cyclone V, arithmetic unit clock rates without extensive pipelining are more in a 50 to 100 MHz range.
Suggest to setup a snippet of your intended logic and experiment with clock rates and pipelining.
Best regards
Frank
New ContributorThank you FvM. Your answer was very helpful. I am going to investigate this issue more carefully with your advice in mind.
ContributorLet me add to the useful suggestions already given by FvM. You CANNOT rely on simple numbers from a datasheet to find the speed at which your design will run. I know this from hard won experience. You MUST create at least a rudimentary design that is representative of the kind of calculation you wish to perform. Create a simple timing constraint and compile the design. The timing analyzer will then TELL YOU what the maximum operating frequency is. If that frequency is too low then you can investigate pipelining, etc. to speed things up. If your requirement is really 500Mhz it sounds like you probably won't get there under any circumstances.
New ContributorExcuse me FvM I need your advice again. Would you like to give me answer on a such a question? You wrote "arithmetic unit clock rates without extensive pipelining are more in a 50 to 100 MHz range". What maximum clock can I operate WITH pipelining? DSP blocks in Cyclone V operate at 250 MHz (according to datasheet). Memory blocks operate at 340-410 MHz. Is the clock limited to 250 MHz? Or I can operate at higher frequency applying pipelining or some other methods?
Super ContributorYou can't exceed 250 MHz - or whatever the maximal clock rate for the respective configuration is - if the design partition uses DSP blocks.
Super ContributorDoes the community helps to answer your question? Do you need further help in regards to this case?
Best Regards,
Richard Tan
New ContributorYes, community helped me. Perhaps I will need futher help in regards to this case.
Super ContributorAny other questions that you would like to ask?
Super ContributorAs we do not receive any response from you on the previous question/reply/answer that we have provided. I now transition this thread to community support.
Feel free to open a new forum thread if you have further question.
Thanks.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
