New Contributor
Super ContributorHello,
did you already look to the datasheet. Under switching characteristics, there's a core performance chapter. Besides maximum core clock, I would particularly refer to DSP and memory block specs. Even if a core clock of e.g. 500 MHz is feasible, you can't operate DSP or memory blocks at this clock rate.
Second point is to find useful clock speed versus logic complexity tradeoff for your design. Length of combinational path between registers defines the maximal clock speed. Pipelining can help to increase speed by dividing logical and arithmetic operations in multiple steps, utilizing additional registers and increasing latency. For Cyclone V, arithmetic unit clock rates without extensive pipelining are more in a 50 to 100 MHz range.
Suggest to setup a snippet of your intended logic and experiment with clock rates and pipelining.
Best regards
Frank
New ContributorExcuse me FvM I need your advice again. Would you like to give me answer on a such a question? You wrote "arithmetic unit clock rates without extensive pipelining are more in a 50 to 100 MHz range". What maximum clock can I operate WITH pipelining? DSP blocks in Cyclone V operate at 250 MHz (according to datasheet). Memory blocks operate at 340-410 MHz. Is the clock limited to 250 MHz? Or I can operate at higher frequency applying pipelining or some other methods?
Super ContributorYou can't exceed 250 MHz - or whatever the maximal clock rate for the respective configuration is - if the design partition uses DSP blocks.
