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Radiowave
New Contributor
New ContributorCyclone V Clock speed
My project for FPGA Cyclone V 5CEFA9F23I7N performs some calculations in between two consecutive IQ samples incoming at frequency 20MHz. In order to have time to calculate everything, I have to set t...
RadiowaveNew Contributor
New ContributorThank you but I think your answer is not what I wanted to know. I'm interested in maximum capabilities of the FPGA. What I managed to find out when I use megawizard for Altera PLL IP core it allows to set input reference PLL clock in the range from 5 to 700 MHz and output PLL clock up to 1600 MHz. I think it`s the answer for my question.
