Cyclone V Clock speed

Thank you but I think your answer is not what I wanted to know. I'm interested in maximum capabilities of the FPGA. What I managed to find out when I use megawizard for Altera PLL IP core it allows to set input reference PLL clock in the range from 5 to 700 MHz and output PLL clock up to 1600 MHz. I think it`s the answer for my question.