Forum Discussion
Radiowave
New Contributor
New ContributorCyclone V Clock speed
My project for FPGA Cyclone V 5CEFA9F23I7N performs some calculations in between two consecutive IQ samples incoming at frequency 20MHz. In order to have time to calculate everything, I have to set t...
RadiowaveNew Contributor
New ContributorExcuse me FvM I need your advice again. Would you like to give me answer on a such a question? You wrote "arithmetic unit clock rates without extensive pipelining are more in a 50 to 100 MHz range". What maximum clock can I operate WITH pipelining? DSP blocks in Cyclone V operate at 250 MHz (according to datasheet). Memory blocks operate at 340-410 MHz. Is the clock limited to 250 MHz? Or I can operate at higher frequency applying pipelining or some other methods?
FvM
Super Contributor
Super ContributorYou can't exceed 250 MHz - or whatever the maximal clock rate for the respective configuration is - if the design partition uses DSP blocks.
