Forum Discussion
New ContributorCyclone V Clock speed
Super ContributorHello,
did you already look to the datasheet. Under switching characteristics, there's a core performance chapter. Besides maximum core clock, I would particularly refer to DSP and memory block specs. Even if a core clock of e.g. 500 MHz is feasible, you can't operate DSP or memory blocks at this clock rate.
Second point is to find useful clock speed versus logic complexity tradeoff for your design. Length of combinational path between registers defines the maximal clock speed. Pipelining can help to increase speed by dividing logical and arithmetic operations in multiple steps, utilizing additional registers and increasing latency. For Cyclone V, arithmetic unit clock rates without extensive pipelining are more in a 50 to 100 MHz range.
Suggest to setup a snippet of your intended logic and experiment with clock rates and pipelining.
Best regards
Frank
New ContributorThank you FvM. Your answer was very helpful. I am going to investigate this issue more carefully with your advice in mind.
GLeesContributor
Let me add to the useful suggestions already given by FvM. You CANNOT rely on simple numbers from a datasheet to find the speed at which your design will run. I know this from hard won experience. You MUST create at least a rudimentary design that is representative of the kind of calculation you wish to perform. Create a simple timing constraint and compile the design. The timing analyzer will then TELL YOU what the maximum operating frequency is. If that frequency is too low then you can investigate pipelining, etc. to speed things up. If your requirement is really 500Mhz it sounds like you probably won't get there under any circumstances.
- Radiowave
Thank you GLees. Your opinion is very valuable and helpful for me.
