Honored ContributorHello,
i would like to know, how I can use interrupts in conjunction with a Cyclone V. (Comparative Avalon) Do you probably have an example for me? I would like to trigger an interrupt using a button. Thanks! Greetings
Honored ContributorYes you can as long as you use a later version of the tools. I forget when they were introduced but 12.1 SP1 or later should have the feature. The HPS has 64 bits of interrupt lines that originate in the FPGA fabric that are sent to the HPS. These interrupt lines connect to the generic interupt controller (GIC) in the MPU subsystem. The MPU subsystem chapter in the device handbook contains the mapping of the FPGA interrupt lines to GIC interrupt numbers, off the top of my head FPGA interrupt [0] connects to GIC interrupt [72]: http://www.altera.com/literature/hb/cyclone-v/cv_54006.pdf
When you connect the PIO to the HPS, use the lightweight HPS-to-FPGA bridge for the memory mapped accesses to the PIO. That lightweight bridge is for accessing CSRs like the PIO. Also the FPGA-to-HPS interrupts are 64-bit but Qsys only supports 32-bit interrupts. As a result the HPS exposes two interrupt receivers, one for the lower 32 bits and the other for the upper 32 bits. Alteratively you can also configure unused HPS I/O as GPIO and use them instead of the FPGA fabric. Each HPS GPIO is capable of generating interrupts as well.Honored ContributorI am using 13.0sp1 and when I enable the 64 fpga2hps interrupt lines, I can't figure out how to make a connection to these interrupt lines. There is no interface created in Qsys and the generated soc_system.v file does not bring these interrupts out to a port. It does create two internal wires:
wire [31:0] hps_f2h_irq0_irq; // irq_mapper:sender_irq -> hps:f2h_irq_p0 wire [31:0] hps_f2h_irq1_irq; // irq_mapper_001:sender_irq -> hps:f2h_irq_p1 and these wires do connect to the hps instantiation, but I don't see how to make an external connection to any of these lines. Compiling the design with these turned on does generate an extra warning: Warning (11713): The configuration of the Hard Processor Subsystem (HPS) within this design has changed. The Preloader software that initializes the HPS requires an update. Using hps_isw_handoff/soc_system_hps/, run the Preloader Support Package Generator to update your Preloader software This warning seems to indicate that the preloader is responsible for setting up these connections, but I'm not sure how to make the connection on the fpga side? Is there another component that needs to be instantiated in qsys? Is there another setting that needs to be done in the hps parameter settings? Is this another feature that is not available with the current tools but will be available in a future release (13.1)?Honored ContributorInterrupt wiring is a little different in Qsys. Over on the right side of your system you should see another patch panel where you can type numbers into them. The numbers normally represents interrupt priority but in the case of the HPS they represent which interrupt bit you are connecting a perheriphals interrupt to out of the group of 32. The interrupt priority is determined by how the generic interrupt controller settings inside the HPS and not the numbers you choose in Qsys, the numbers are just determining connectivity.
Honored ContributorYes, of course. I see the interrupt connection you're talking about in Qsys. Thanks.
Honored ContributorHello,
I'm currently trying to make use of the FPGA -> HPS interrupt lines as well and I'm running into issues. In summary, I have interrupts coming in from the FPGA on FPGA_IRQ0 and FPGA_IRQ1 (GIC interrupts 72 and 73) and an IRQ handler registered for these same lines. However, I never see the interrupts appear in Linux. See the below cat /proc/interrupts (my module is "fpgaint"): CPU0 CPU1 29: 15752236 15740759 GIC twd 72: 0 0 GIC fpgaint0 73: 0 0 GIC fpgaint1 147: 47023 0 GIC eth0 160: 1 0 GIC dwc_otg, dwc_otg_hcd:usb1 171: 2052 0 GIC dw-mci By peeking around the ARM GIC registers, I verified that the triggering is set properly according to the nodes I placed in the device tree (edge triggered) and that the interrupts are in fact enabled. So at this point I'm confident that the Linux setup and the ARM GIC setup are correct. I've read the GIC interrupt status register as well and never see my interrupt lines go high. I'm currently working with our hardware engineer to verify the interrupt lines are going high from the FPGA side using SignalTap. I noticed in the above discussion that after enabling these interrupt lines in the FPGA build, the preloader needed to be regenerated. I looked through the handoff files and I don't see anything that corresponds to these interrupt lines. Overall, I have the below questions:Honored ContributorI can't speak for the software side but for the hardware there is no need to release the bridges for IRQs from the FPGA to propogate through to the GIC in the HPS. The IRQs from the FPGA are considered asynchronous so they undergo clock domain crossing followed by edge detection so you might need a wider IRQ pulse from the FPGA side. What clock frequency do you use the MPU and the FPGA logic generating the interrupt, and how many clock cycles does the FPGA logic assert the IRQ for?
Honored Contributor" Over on the right side of your system you should see another patch panel where you can type numbers into them."
I am sorry but I am not immediately seeing a place where I can type numbers on the right side. Has this changed in 13.1, or can somebody maybe post a screenshot ? Or should something be enabled first before you get this option ?Honored ContributorYou might need to scroll the system panel to the right to see it. It'll be a column to the right of the HPS and all the other components in your system. You might also have interrupts filtered from the UI so if you click the filter button you can expose the interrupts (I normally just click the "all" filter so that I can see everything).
Last but not lease make sure the interrupt interface for the HPS is enabled in the HPS component, otherwise those interrupt lines will not be exposed in Qsys.Honored ContributorI am not at the setup right now so this is from memory, but we can see a column named IRQ(s), it is just now obvious what we can do with it.
There are some short horizontal lines/diamonds(?) in it at some locations , but there not immediately an obvious way to make a connection between them and the HPS component. Based on your comment we started looking for some kind of input field for numbers, but we can't see that either. Probably we are just overlooking something very obvious (sorry ;p), I will try to add a screenshot tomorrow. >Last but not lease make sure the interrupt interface for the HPS is enabled in the HPS component, otherwise those interrupt lines will not be exposed in Qsys. By that you mean 'Enable FPGA-to-HPS Interrupts' as eg mentioned in http://www.altera.com/literature/hb/cyclone-v/cv_54027.pdf p 27-6, right ? (this is enabled)Honored ContributorThe interrupt column represents connectivity. The HPS exposes two 32-bit interrupt receivers (input) and you connect the interrupt sender (output) from the peripherals to either of the HPS interrupt receivers. Once connected you can type a number between 0 and 31 in the interrupt connection to specify the interrupt mapping. irq receiver 0 interrupts between 0-31 map the HPS GIC interrupts 72-103 and irq receiver 1 interrupts between 0-31 map to HPS GIC interrupts 104-135.
You might be wondering why there are two interrupt recievers, it's a limitation of Qsys that an interrupt reciever can only be up to 32-bits wide. So because the HPS exposes 64 interrupts it was split into two interrupt reciever interfaces. My recommendation would be to look at an existing design like the golden hardware reference design so that you can see how the interrupts are connected in it. Just make note of which interrupt numbers you choose in Qsys since that determines which GIC interrupt number will be used. You can find the GIC numbers in table 6-2 in this chapter: http://www.altera.com/literature/hb/cyclone-v/cv_54006.pdf
