Cyclone V - Interrupt Handling

Hello,

I'm currently trying to make use of the FPGA -> HPS interrupt lines as well and I'm running into issues. In summary, I have interrupts coming in from the FPGA on FPGA_IRQ0 and FPGA_IRQ1 (GIC interrupts 72 and 73) and an IRQ handler registered for these same lines. However, I never see the interrupts appear in Linux. See the below cat /proc/interrupts (my module is "fpgaint"):

CPU0 CPU1

29: 15752236 15740759 GIC twd

72: 0 0 GIC fpgaint0

73: 0 0 GIC fpgaint1

147: 47023 0 GIC eth0

160: 1 0 GIC dwc_otg, dwc_otg_hcd:usb1

171: 2052 0 GIC dw-mci

By peeking around the ARM GIC registers, I verified that the triggering is set properly according to the nodes I placed in the device tree (edge triggered) and that the interrupts are in fact enabled. So at this point I'm confident that the Linux setup and the ARM GIC setup are correct. I've read the GIC interrupt status register as well and never see my interrupt lines go high. I'm currently working with our hardware engineer to verify the interrupt lines are going high from the FPGA side using SignalTap.

I noticed in the above discussion that after enabling these interrupt lines in the FPGA build, the preloader needed to be regenerated. I looked through the handoff files and I don't see anything that corresponds to these interrupt lines.

Overall, I have the below questions:

1. What exactly needs to be done at the initialization stage by the preloader to enable these interrupt paths?

2. Which variables get modified in the handoff files when these interrupt lines are enabled (so I can trace to ensure my preloader is handling this)?

3. Is there anything else that comes to mind that might be going wrong here? Do some bridges need to be released from reset?

4. I don't know anything about FPGA code but is there any special way that these interrupts have to be generated? Or is simply pulsing that line sufficient for edge triggered configuration?

I appreciate any guidance either of you could give.

Thanks,

-Chris