Cyclone V - Interrupt Handling

I can't speak for the software side but for the hardware there is no need to release the bridges for IRQs from the FPGA to propogate through to the GIC in the HPS. The IRQs from the FPGA are considered asynchronous so they undergo clock domain crossing followed by edge detection so you might need a wider IRQ pulse from the FPGA side. What clock frequency do you use the MPU and the FPGA logic generating the interrupt, and how many clock cycles does the FPGA logic assert the IRQ for?