Cyclone V - Interrupt Handling

Yes you can as long as you use a later version of the tools. I forget when they were introduced but 12.1 SP1 or later should have the feature. The HPS has 64 bits of interrupt lines that originate in the FPGA fabric that are sent to the HPS. These interrupt lines connect to the generic interupt controller (GIC) in the MPU subsystem. The MPU subsystem chapter in the device handbook contains the mapping of the FPGA interrupt lines to GIC interrupt numbers, off the top of my head FPGA interrupt [0] connects to GIC interrupt [72]: http://www.altera.com/literature/hb/cyclone-v/cv_54006.pdf

When you connect the PIO to the HPS, use the lightweight HPS-to-FPGA bridge for the memory mapped accesses to the PIO. That lightweight bridge is for accessing CSRs like the PIO. Also the FPGA-to-HPS interrupts are 64-bit but Qsys only supports 32-bit interrupts. As a result the HPS exposes two interrupt receivers, one for the lower 32 bits and the other for the upper 32 bits.

Alteratively you can also configure unused HPS I/O as GPIO and use them instead of the FPGA fabric. Each HPS GPIO is capable of generating interrupts as well.