Cyclone V - Interrupt Handling

The interrupt column represents connectivity. The HPS exposes two 32-bit interrupt receivers (input) and you connect the interrupt sender (output) from the peripherals to either of the HPS interrupt receivers. Once connected you can type a number between 0 and 31 in the interrupt connection to specify the interrupt mapping. irq receiver 0 interrupts between 0-31 map the HPS GIC interrupts 72-103 and irq receiver 1 interrupts between 0-31 map to HPS GIC interrupts 104-135.

You might be wondering why there are two interrupt recievers, it's a limitation of Qsys that an interrupt reciever can only be up to 32-bits wide. So because the HPS exposes 64 interrupts it was split into two interrupt reciever interfaces.

My recommendation would be to look at an existing design like the golden hardware reference design so that you can see how the interrupts are connected in it. Just make note of which interrupt numbers you choose in Qsys since that determines which GIC interrupt number will be used. You can find the GIC numbers in table 6-2 in this chapter: http://www.altera.com/literature/hb/cyclone-v/cv_54006.pdf