Honored Contributor
Honored ContributorI am using 13.0sp1 and when I enable the 64 fpga2hps interrupt lines, I can't figure out how to make a connection to these interrupt lines. There is no interface created in Qsys and the generated soc_system.v file does not bring these interrupts out to a port. It does create two internal wires:
wire [31:0] hps_f2h_irq0_irq; // irq_mapper:sender_irq -> hps:f2h_irq_p0 wire [31:0] hps_f2h_irq1_irq; // irq_mapper_001:sender_irq -> hps:f2h_irq_p1 and these wires do connect to the hps instantiation, but I don't see how to make an external connection to any of these lines. Compiling the design with these turned on does generate an extra warning: Warning (11713): The configuration of the Hard Processor Subsystem (HPS) within this design has changed. The Preloader software that initializes the HPS requires an update. Using hps_isw_handoff/soc_system_hps/, run the Preloader Support Package Generator to update your Preloader software This warning seems to indicate that the preloader is responsible for setting up these connections, but I'm not sure how to make the connection on the fpga side? Is there another component that needs to be instantiated in qsys? Is there another setting that needs to be done in the hps parameter settings? Is this another feature that is not available with the current tools but will be available in a future release (13.1)?
