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YogeshaDG's avatar
YogeshaDG
Icon for New Contributor rankNew Contributor
23 days ago

Cyclone IV E(EP4CE30) FPGA JTAG and USB-Blaster

Hi Team,

I am working with a Cyclone IV E FPGA(EP4CE30), where all my banks (Bank 1–8) have VCCIO = 3.3V. The FPGA core voltage is 1.2V, and the PLL supply is 2.5V. I am configuring the FPGA in Passive Serial (PS) mode.

My current doubt is regarding the pull-up voltage for JTAG and USB Blaster:
Should the pull-up resistors be tied to 2.5V or 3.3V? What should be the pullup voltage for MSEL Pin..?

As per the Hardware Design Guidelines, my understanding is that the pull-up supply should match the VCCIO of the respective bank. Please confirm if this is correct.

For your review, I have attached a snippet of the Configuration Pin Schematic. Kindly check and let me know if anything looks incorrect.

Additionally, for the 10-pin male header, what should be the voltage level for Pin 4 and Pin 6?

Please respond at the earliest. If you need any clarification, feel free to ask.

Thank you!

 

Configuration
Core Logic
Power
Programmable Logic Device

7 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    23 days ago

    Hi,

    device handbook suggests to use 2.5 V supply (VCCA) for JTAG interface (pull-ups and connector pin 4) with 3.3 V supplied JTAG IO bank.

    Purpose is avoiding overshoot above maximum input voltage rating of 4.1 V. 

    Regards Frank

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    18 days ago

    Hi,

     

    This is the reference from the Cyclone IV Handbook for PS configuration mode using the download cable.

    It shows the pull-up voltage for the USB blaster as well as the MSEL pin. It also shows the connection guideline for Pin 4 and 6 of the Male Header

    For further information, you can refer to the handbook.

    • YogeshaDG's avatar
      YogeshaDG
      Icon for New Contributor rankNew Contributor
      15 days ago

      Hi, 

      i have referred this Handbook for Cyclone 4E, my doubt is that, all my I/O banks VCC's are 3.3V and here they have given pullup voltage reference as VCCA.  all these configurations pins are available in Bank 1 and Bank 6, and there respective VCCIO is 3.3V. if i gave pullup voltage VCCA of 2.5V to this lines, is there any problem occurs, or is it okay to provide any of the one (3.3V or 2.5v)..?

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    16 days ago

    Dear Customer,

    Let me know if you have any additional questions. 

    I will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

    Thank you for engaging with us!

    Best regards,
    Altera Technical Support

      • YogeshaDG's avatar
        YogeshaDG
        Icon for New Contributor rankNew Contributor
        8 days ago

        Hi, thanks for the quick support.

        I assume we will follow the same approach for the configuration pins as well. I am planning to configure the Cyclone IV E FPGA in Passive Serial (PS) mode using:

        • Single-Device PS Configuration Using an External Host (as shown in Figure 8–13)
        • PS Configuration Using a Download Cable (as shown in Figure 8–17)

        I believe the pull-up resistor should be connected to VCCA (2.5 V). If you have any concerns or suggestions regarding this, please share your thoughts.

        i have attached my draft schematic for your reference.