Cyclone 3 Not entering AS Mode

Without knowing the hardware setup of the board (is it a dev kit or custom?) or seeing the original project (this is just a programming file you've attached instead of the Quartus project), it's going to be difficult for anybody to help you out. If it's a dev kit, mention which one it is. If it's custom, provide schematics to see the connection and setup between the device and the flash.

Thanks @sstrell for the response. Attached is my circuit. A bit of a history. Circuit was a built a while back and it was working. Circuit was built again recently and the issue started and we don't where to start. Pad is grounded and we have all the Pull up and Pull downs. we built multiple and still having the issue. Not sure if there is something we need to do to put the circuit on AS mode. From what we can see, it is not getting into AS mode

Your post here says you're using an EPCQ16A, but your schematic says you're using a much older EPCS16. Have you just created the programming file for the wrong device?

Since EPCS is not available anymore, we switch to EPCQ16 which is supposed to be compactible. Even without using the memory chip, it seems like we are not getting any clock from DCLK which from reading the documentation will not have anything to do with the memory chip we are using. We are just trying to run a simple programming file that outputs frequency so that we can see it in TX to verify that things are well. Also we cant program AS at all.

If you're not seeing the 30 or 40 MHz output on DCLK, maybe the device is damaged, causing a problem with the internal oscillator that drives DCLK. Is this a single board or happening on multiples?

You probably need to be going though the handbook and check things like power supplies, pull-ups and pull-downs, etc. Something is not right.

https://www.intel.com/content/www/us/en/content-details/654357/cyclone-iii-device-handbook.html

Hi,
I think some details of the error report are still unclear. What's meant e.g. with "I was having an issue with jtag and I grounded the pad." Grounded which pad?

I generally agree with sstrell that i looks much like a problem of correct PCB wiring and signal integrity.

Not sure if the FPGA relatic schematic part is shown completely. I'm missing e.g. JTAG pull-up/-down resistors. Particularly missing 1k TCK pull-down can cause erratic operation of JTAG logic and e.g. block AS configuration. The schematic shows about no supply bypass capacitors, this can cause serious issues depending on PCB layout. But I won't finally assess possible power and signal integrity problems without seeing full schematic and layout.

First step of AS circuit test is successful JTAG indirect flash programming and verification. If this doesn't work, it's rather unlikely to get AS configuration loaded.

A specific question was about DCLK operation. DCLK is driven by the FPGA during AS configuration. In addition, Intel AS programming IP (e.g. ASMI) is sending continuous DCLK. Unless you instantiate respective IP in your design, DCLK shoul be quiet in user mode.

Regards
Frank

Hello,

Could you please provide the scopeshot for below signals?

1. nCONFIG
2. CONF_DONE
3. nSTATUS
4. VCC (during ramp up)

all with the same timeframe. We can check what stage the device fail and troubleshoot from there.

regards,

Farabi

Please can someone help me with this issue? I have been stuck on this for over 2 months now. According to the documentation, Cyclone 3 family should always oscillate on DCLK at least 40MHZ. Am barely getting 700khz. I have bought multiple cyclone chips and changed and still no difference. How do i trigger the internal oscillator?

Hi Kodion22,

Any updates on this issue? Based on your previous statement that no problems occurs on the older boards, it is highly due to the isssue with a new board's design. Could you identify the key changes between the old and the new boards?

Regards,

Fakhrul