New Contributor
Super ContributorHi,
I think some details of the error report are still unclear. What's meant e.g. with "I was having an issue with jtag and I grounded the pad." Grounded which pad?
I generally agree with sstrell that i looks much like a problem of correct PCB wiring and signal integrity.
Not sure if the FPGA relatic schematic part is shown completely. I'm missing e.g. JTAG pull-up/-down resistors. Particularly missing 1k TCK pull-down can cause erratic operation of JTAG logic and e.g. block AS configuration. The schematic shows about no supply bypass capacitors, this can cause serious issues depending on PCB layout. But I won't finally assess possible power and signal integrity problems without seeing full schematic and layout.
First step of AS circuit test is successful JTAG indirect flash programming and verification. If this doesn't work, it's rather unlikely to get AS configuration loaded.
A specific question was about DCLK operation. DCLK is driven by the FPGA during AS configuration. In addition, Intel AS programming IP (e.g. ASMI) is sending continuous DCLK. Unless you instantiate respective IP in your design, DCLK shoul be quiet in user mode.
Regards
Frank
New ContributorI am able to program the FPGA via JTAG. I can successfully upload code with no issue. My issue right now is getting AS to work. I do have the AS pin for the blaster but when i connect my blaster to it, i get error about silicon id. From what all i can read, it seems like the FPGA is not going to AS mode. Am not sure what all can cause it.
Ground pad means, putting a wire through the ground pad of my Cyclone and connect it to ground.
More insight.. The circuit was built in 2007 and it has been working. We did a latest redesign to be able to use newer components. So basically i want to gain the knowledge to troubleshoot better since am not certain is from the circuit since this has been working for years on the older boards
What frequency should i get on my DCLK pin when the board is plug up and the memory chip is on the board? I believe there should be continues clock even when you are not doing any AS programming in Quartus. Nowadays some people can load code into the memory chip using a tool and solder it into the board. So if the memory chip has the program, wouldn't the FPGA pick it up via the DATA pin?
Again, am new to all this. So pardon me if am not using the right words
