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New ContributorCyclone 3 Not entering AS Mode
New ContributorPlease can someone help me with this issue? I have been stuck on this for over 2 months now. According to the documentation, Cyclone 3 family should always oscillate on DCLK at least 40MHZ. Am barely getting 700khz. I have bought multiple cyclone chips and changed and still no difference. How do i trigger the internal oscillator?
Super Contributoryou wrote recently: "According to the documentation, Cyclone 3 family should always oscillate on DCLK at least 40MHZ. Am barely getting 700khz."
DCLK is not generally oscillating in Cyclone III AS configuration. Which document are you referring to?
DCLK is operating during configuration load and stops after starting user mode, except for a special case mentioned above.
Presumed the AS flash is correctly connected to FPGA and configuration mode set to AS, the flash can be programmed and verified in JTAG indirect mode.
- Kodion22
I hope am not misunderstanding the documentation. Here is the reference attached. I also attached the screenshot. Also i have an old evulation board and when i probe the DCLK it is about 40MHZ. It is also a cyclone 3 but a different family than mine.
what do you mean by Presumed the AS flash is correctly connected to FPGA and configuration mode set to AS, the flash can be programmed and verified in JTAG indirect mode"
- FvM
Hi,
the handbook quote talks about expectable DCLK frequency when operting, not about continuous clock. During initial configuration load, DCLK isn't running continuously. The "old evaluation board" has possibly SFL IP compiled into the design, special case discussed above.
JTAG indirect programming uses figure 9-30 according to Cyclone III handbook.
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