Forum Discussion

ChathEsh's avatar
ChathEsh
Icon for New Contributor rankNew Contributor
1 year ago

Cyclone 10 LP VccIO

I have a Cyclone 10 LP based design where VccIO of one of the IO banks is being supplied by a 3.3V, but the output pins are configured as 1.8V. This is caused by use of same firmware in different hardware configurations. These 1.8V logic pins are 'no connect' (does not connect to any other devices) when 3.3V VccIO is applied on bank . Is this safe?

The only documentation that we could find in support for this is

But this info does not guarantee if it is acceptable to drive the VccIO with a higher voltage than the logic of pins selected in the pin constraints.

The device that we use is 10CL010YM164I7G.

Configuration
Generic Io

5 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago
    Should be safe. Bank voltage settings are used to configure output drive strength. Outputs can be overloaded if you set higher drive strength than allowed for 3.3 V and connect low impedance load.
  • ChathEsh's avatar
    ChathEsh
    Icon for New Contributor rankNew Contributor
    1 year ago

    Thank you for the quick response @FvM . Is it the same single ended output stage that is used regardless of what single ended logic type is selected in the constraint? In that case the logic level defined in the pin constraint file is more for timing and similar analysis?

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Output involves multiple driver transistors to implement different drive strengths. In so far, hardware can be configured differently.

  • NazrulNaim_Intel's avatar
    NazrulNaim_Intel
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    I'm agree with the answer provided from user 'FvM", but based on the official document, it is not recommended to use the connection like this, but it is not restricted. This is because based on the official documentation, the NC pin should not be connected. More information regarding on the connection guideline can be accessed through the link below.


    Link : https://cdrdv2.intel.com/v1/dl/getContent/670726?fileName=pcg-01021-683137-670726.pdf


    Hope that answers your question.


    Best regards,

    Nazrul Naim


  • NazrulNaim_Intel's avatar
    NazrulNaim_Intel
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,

    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

    Best regards,

    Nazrul Naim