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ChathEsh's avatar
ChathEsh
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2 years ago

Cyclone 10 LP VccIO

I have a Cyclone 10 LP based design where VccIO of one of the IO banks is being supplied by a 3.3V, but the output pins are configured as 1.8V. This is caused by use of same firmware in different har...
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Generic Io
ChathEsh's avatar
ChathEsh
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2 years ago

Thank you for the quick response @FvM . Is it the same single ended output stage that is used regardless of what single ended logic type is selected in the constraint? In that case the logic level defined in the pin constraint file is more for timing and similar analysis?