yes2
New Contributor
1 year agoCyclone 10 LP configuration/JTAG pin VCCIO
Hi, I am designing a PCB that uses a Cyclone 10 LP. Due to PCB space constraints, I was planning on leaving 2 IO banks on the FPGA unconnected to VCCIO (or at least without any decoupling capacitors).
One of the banks I'm not using contains the programming configuration pins (INIT_DONE etc), are these I/O's powered through the VCCIO of the relevant bank? In which case I would have to connect the VCCIO of the bank (but can likely get away with using very little decoupling capacitors due to low switching speed).
Thank you!