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yes2's avatar
yes2
Icon for New Contributor rankNew Contributor
1 year ago

Cyclone 10 LP configuration/JTAG pin VCCIO

Hi, I am designing a PCB that uses a Cyclone 10 LP. Due to PCB space constraints, I was planning on leaving 2 IO banks on the FPGA unconnected to VCCIO (or at least without any decoupling capacitors)...
Board Debug
Generic Io
Power
FakhrulA_altera's avatar
FakhrulA_altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi yes2,


I wish to follow up with you on this case. Do you still have further inquiries on this issue? Please feel free to let me know if there is any concern so that we could further assist you.


Regards,

Fakhrul