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yes2's avatar
yes2
Icon for New Contributor rankNew Contributor
1 year ago

Cyclone 10 LP configuration/JTAG pin VCCIO

Hi, I am designing a PCB that uses a Cyclone 10 LP. Due to PCB space constraints, I was planning on leaving 2 IO banks on the FPGA unconnected to VCCIO (or at least without any decoupling capacitors)...
Board Debug
Generic Io
Power
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago
Please refer to user manual
"The POR circuit of the Intel Cyclone 10 LP device monitors the VCCINT, VCCA, and VCCIO (of banks 1, 5, 6, and that contain configuration pins during power-on. You can power up or power down the VCCINT, VCCA, and VCCIO pins in any sequence. The VCCINT, VCCA, and VCCIO must have a monotonic rise to their steady state levels. All VCCA pins must be powered to 2.5V (even when phase-locked loops [PLLs] are not used), and must be powered up and powered down at the same time."