Create NIOS system with SRAM

When you don't know what to do, look at the examples. There are plenty of them for academic or development boards.

You need to create a SOPC (this one is old) or QSYS system, add path to *.qip file in Quartus project and create a top level file where you QSYS is instantiated. Connect QSYS inputs and outputs in your top level to physical pins.

Hi, linas.

I already tryed everything I could. I only post something in forum, when I realy don't know what to do.

Now I read in /showthread.php?t=6255 that IDT71V416 is created for some other boards. I followed the steps MSchmitt diskribed in post 3 and connected my tristate slave sram_0 to Avalon MM Tristate Bridge. NIOS instruction and data master both connected to the bridge. As that was done, I got SoPC buider warning "sram_controller_0: sram_controller_0.avalon_tristate_slave_1 must be exported, or connected to a matching conduit." I guess it's ok, I just connected the signals to the pins in my top level .vhd:

addr_to_the_sram_comtroller_0 => SRAM_ADDR,

data_to_and_from_the_sram_comtroller_0 => SRAM_DQ,

write_n_to_the_sram_comtroller_0 => SRAM_WE_N,

read_n_to_the_sram_comtroller_0 => SRAM_OE_N,

chipselect_n_to_the_sram_comtroller_0 => SRAM_CE_N

Now I can't see memory region in eclipse IDE. I've added this in the BSP editor manually and changed stack from on_chip to sram just for a test. Of course it doesn't work. What am I doing wrong (I guess a lot of stuff)? Please someone take some time and discribe a beginner what to do, totaly stuck here.

Thanks.

I think, this topic is more important to you: http://www.alteraforum.com/forum/showthread.php?t=26505

You need to write a controller for your SRAM. Avalon slave on one end and SRAM interface on the other one. Or find somewhere on the net. SRAM isn't complex since it does not need refresh.

Thank you, Sir.

Suddenly things become realy good. Since I have 50mhz clock, I dont have to wait any clock cycles for read or write beacause according to sram dataseet it only takes 10ns to read and 8ns to write. So I just do this:

coe_SRAM_WE_N <= avs_write_n;

coe_SRAM_DQ <= avs_writedata when avs_write_n = '0' else (others => 'Z');

avs_readdata <= coe_SRAM_DQ;

coe_SRAM_ADDR <= avs_address;

coe_SRAM_UB_N <= avs_byteenable_n;

coe_SRAM_LB_N <= avs_byteenable_n;

coe_SRAM_OE_N <= avs_read_n;

coe_SRAM_CE_N <= avs_read_n and avs_write_n;

in my sram architecture and it works so far. I got ony one more question.

coe_SRAM_UB_N <= avs_byteenable_n;

coe_SRAM_LB_N <= avs_byteenable_n;

This is not realy smart, right? What do I have to do with this signal? My datawidth is 8bit. Can I simply ignore this signals and pins? When I ignore them, what then to do with byteenable?

Thanks a lot once more, linas.

Hi, linas. Thanks again for reply. I got this now.

No, byteenable is datawidth/8, so it is 1bit since my datawidth is 8, so byteenable is indeed useless, at least in this case. But if I implement my avs without byteenable, I become a warning while SoPC system generation. Maybe it's bug and Qsys complain. Now I just extended slave addresswidth to 21 and use the lsb to select LB/UB. I still have byteenable in my port list but I don't use it. For anyone who's interested I upload the .vhd file. Please tell if you see something stupid :D

Regards!

Hi.

Have another problem with (I think) same sram controller.

What I want to do is access SRAM and SDRAM from my custom peripheral for read and write actions. Now I connected read and write MM-Masters to this memory in SoPC-Builder, generated, compiled.... But there seems to be something wrong, I just get wrong values written on memory. As I read http://www.cas.mcmaster.ca/~lawford/3tb4/ref/avalon1.pdf page 4, I implemented avs_chipselect in my sram-controller logic. I thought that was my mistake and the avalon interconnection fabric will now set chipselect just as it shown in linked document Figute 2-2. In my sram.vhd changed not much, just the declaration of avs_chipselect and

coe_SRAM_CE_N <= avs_read_n and avs_write_n when avs_chipselect = '1' else '1';

But now nothing works as as I move .data, .stack.... to SRAM

So how is it possible to read or write to different slaves with one master? I don't realy know if I'm right with this chipselect signal, it seems like the address decode logic controlls it but then it should work.....or not? Also I'm surprised that the sram without chipselect works rerrectly, I mean NIOS II data and instruction master are connected to several slaves as well. I tryed to get through the arbitators and cpu data master connection to get the point why it works but this 9000+ automatic created lines of code just blown my mind.

I'm realy confused right now. Hope someone helps. Thank you.

Vlad.

The avs_read_n and avs_write_n signals are only asserted when your slave is selected, so you don't need to use avs_chipselect. IIRC the chipselect signal has been deprecated and it's not sure it is supported properly in the latest versions.

To debug your system it is easier to use probes such as Signaltap than trying to go through the generated code.

The documentation you linked to is rather old. Please use the avalon specification (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf) instead, which is more up to date.

You do need to look at the byte enable signal - especially for writes.

A transfer from a 32bit Avalon master (eg a nios cpu) goes through a 'bus width adapter' that will always perform 4 cycles on you 8-bit slave. For a byte write three of them will have the byte enable deasserted.

While it is probably possible to feed the avalon address directly to your SRAM and latch the read data whenever a read is requested, you almost certainly can't do the same for writes.

The write_n signal is only valid on the relevant clock edge - so you must latch the address/data and do the actual write in the following clock cycle.

Hi. Thank you for reply.

It actualy works with chipselect, hat just to refresh system in sopc-builder and regenerate. As it was done I was able to link all datasegments to SRAM and run some printf() as test. But it still does wrong read/write operations with my custom peripheral. Also I think you understood me wrong, probably because of my bad english and explain stuff skills. Sorry for that.

Ok, I'll try it once more. I've written a custom DMA with 3 components, MM-Slave, MM-Master for read operations and an MM-Master for write. As soon as the slave gets source address and destination address followed by a go DMA starts read and write. It works for SRAM and SDRAM well, but what I want to do is write data to different memorys. As soon as I connect write master to both, SRAM and SDRAM, DMA writes wrong data. I thought I need chipselect to deactivate SRAM when I want to write to SDRAM. Correct me if I'm wrong but read_n and write_n from my DMA won't actualy be desserted for SRAM when address is in SDRAM area. Before that I've tried to implement two write masters but then it was also wrong.

So my question is, when not chipselect, how the actual needed slave component is activated? I think if I connect my DMA to SRAM and SDRAM, SRAM will be activated as soon as I assert read_n or write_n, no matter which address I want to write/read to.

Hope you understood me.

Thanks.

Vlad

Edit: I found

--- Quote Start ---

Qsys generates a interconnection fabric which filters "read" and "write" signals from the masters accordingly to the address and the address map.

So, a slave only sees "read" and "write" signals intended for them, not for other slaves.

No clue what the chipselect signal was even intended for.

--- Quote End ---

Unfortunatly I work with SoPC-Builder Quartus 12.0sp2. Didn't found anything about chipselect for SoPC-Builder except the document from my previos post. Does anyone know if I need this signal?