Create NIOS system with SRAM

Hi.

Have another problem with (I think) same sram controller.

What I want to do is access SRAM and SDRAM from my custom peripheral for read and write actions. Now I connected read and write MM-Masters to this memory in SoPC-Builder, generated, compiled.... But there seems to be something wrong, I just get wrong values written on memory. As I read http://www.cas.mcmaster.ca/~lawford/3tb4/ref/avalon1.pdf page 4, I implemented avs_chipselect in my sram-controller logic. I thought that was my mistake and the avalon interconnection fabric will now set chipselect just as it shown in linked document Figute 2-2. In my sram.vhd changed not much, just the declaration of avs_chipselect and

coe_SRAM_CE_N <= avs_read_n and avs_write_n when avs_chipselect = '1' else '1';

But now nothing works as as I move .data, .stack.... to SRAM

So how is it possible to read or write to different slaves with one master? I don't realy know if I'm right with this chipselect signal, it seems like the address decode logic controlls it but then it should work.....or not? Also I'm surprised that the sram without chipselect works rerrectly, I mean NIOS II data and instruction master are connected to several slaves as well. I tryed to get through the arbitators and cpu data master connection to get the point why it works but this 9000+ automatic created lines of code just blown my mind.

I'm realy confused right now. Hope someone helps. Thank you.

Vlad.