Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Create NIOS system with SRAM

Hi. I started to work with FPGA and Altera system about 2 month ago and as soon as I thought I start to understand something, I'm in dead end.....AGAIN! I think my problem is still that I don't...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I think, your avs_byteenable_n is a two bit bus. In this case avs_byteenable_n(1) should go to coe_SRAM_UB_N and avs_byteenable_n(0) to coe_SRAM_LB_N. Personally I prefer not to use byteenable type signals, because they just add development overhead and are mostly useless.