Create NIOS system with SRAM

Hi. Thank you for reply.

It actualy works with chipselect, hat just to refresh system in sopc-builder and regenerate. As it was done I was able to link all datasegments to SRAM and run some printf() as test. But it still does wrong read/write operations with my custom peripheral. Also I think you understood me wrong, probably because of my bad english and explain stuff skills. Sorry for that.

Ok, I'll try it once more. I've written a custom DMA with 3 components, MM-Slave, MM-Master for read operations and an MM-Master for write. As soon as the slave gets source address and destination address followed by a go DMA starts read and write. It works for SRAM and SDRAM well, but what I want to do is write data to different memorys. As soon as I connect write master to both, SRAM and SDRAM, DMA writes wrong data. I thought I need chipselect to deactivate SRAM when I want to write to SDRAM. Correct me if I'm wrong but read_n and write_n from my DMA won't actualy be desserted for SRAM when address is in SDRAM area. Before that I've tried to implement two write masters but then it was also wrong.

So my question is, when not chipselect, how the actual needed slave component is activated? I think if I connect my DMA to SRAM and SDRAM, SRAM will be activated as soon as I assert read_n or write_n, no matter which address I want to write/read to.

Hope you understood me.

Thanks.

Vlad

Edit: I found

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Qsys generates a interconnection fabric which filters "read" and "write" signals from the masters accordingly to the address and the address map.

So, a slave only sees "read" and "write" signals intended for them, not for other slaves.

No clue what the chipselect signal was even intended for.

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Unfortunatly I work with SoPC-Builder Quartus 12.0sp2. Didn't found anything about chipselect for SoPC-Builder except the document from my previos post. Does anyone know if I need this signal?