Create NIOS system with SRAM

You do need to look at the byte enable signal - especially for writes.

A transfer from a 32bit Avalon master (eg a nios cpu) goes through a 'bus width adapter' that will always perform 4 cycles on you 8-bit slave. For a byte write three of them will have the byte enable deasserted.

While it is probably possible to feed the avalon address directly to your SRAM and latch the read data whenever a read is requested, you almost certainly can't do the same for writes.

The write_n signal is only valid on the relevant clock edge - so you must latch the address/data and do the actual write in the following clock cycle.