Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Create NIOS system with SRAM

Hi. I started to work with FPGA and Altera system about 2 month ago and as soon as I thought I start to understand something, I'm in dead end.....AGAIN! I think my problem is still that I don't...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi, linas. Thanks again for reply. I got this now.

No, byteenable is datawidth/8, so it is 1bit since my datawidth is 8, so byteenable is indeed useless, at least in this case. But if I implement my avs without byteenable, I become a warning while SoPC system generation. Maybe it's bug and Qsys complain. Now I just extended slave addresswidth to 21 and use the lsb to select LB/UB. I still have byteenable in my port list but I don't use it. For anyone who's interested I upload the .vhd file. Please tell if you see something stupid :D

Regards!