Create NIOS system with SRAM

Thank you, Sir.

Suddenly things become realy good. Since I have 50mhz clock, I dont have to wait any clock cycles for read or write beacause according to sram dataseet it only takes 10ns to read and 8ns to write. So I just do this:

coe_SRAM_WE_N <= avs_write_n;

coe_SRAM_DQ <= avs_writedata when avs_write_n = '0' else (others => 'Z');

avs_readdata <= coe_SRAM_DQ;

coe_SRAM_ADDR <= avs_address;

coe_SRAM_UB_N <= avs_byteenable_n;

coe_SRAM_LB_N <= avs_byteenable_n;

coe_SRAM_OE_N <= avs_read_n;

coe_SRAM_CE_N <= avs_read_n and avs_write_n;

in my sram architecture and it works so far. I got ony one more question.

coe_SRAM_UB_N <= avs_byteenable_n;

coe_SRAM_LB_N <= avs_byteenable_n;

This is not realy smart, right? What do I have to do with this signal? My datawidth is 8bit. Can I simply ignore this signals and pins? When I ignore them, what then to do with byteenable?

Thanks a lot once more, linas.