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Altera_Forum
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15 years ago

Conversion uses all combinational logic

Hi,

I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip. 


type DATE_ARRAY is array(5 downto 0) of integer range 0 to 2100;
variable SC_Var : std_logic_vector(7 downto 0) := x"00";
        variable MN_Var : std_logic_vector(7 downto 0) := x"00";
        variable HR_Var : std_logic_vector(7 downto 0) := x"00";
        variable DT_Var : std_logic_vector(7 downto 0) := x"00";
        variable MO_Var : std_logic_vector(7 downto 0) := x"00";
        variable YR_Var : std_logic_vector(7 downto 0) := x"00";
        variable DW_Var : std_logic_vector(7 downto 0) := x"00";
date := ntpToRTC(timestamp_var);
                                SC_Var := std_logic_vector(to_unsigned(date(0),8));
                                MN_Var := std_logic_vector(to_unsigned(date(1),8));
                                HR_Var := std_logic_vector(to_unsigned(date(2),8)) or x"80";
                                DT_Var := std_logic_vector(to_unsigned(date(3),8));
                                MO_Var := std_logic_vector(to_unsigned(date(4),8));
                                YR_Var := std_logic_vector(to_unsigned(date(5),8));
                                DW_Var := "00000000";

The function I call fills the data with integers representing year, month, day... I also tried putting each conversion in a sepearate state and it made no difference.

Any help much appreciated

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Its the functions that add all of the dividers, that kill your FMAx down to 1.5MHz, because none of them are clocked (you are calculating all those values in a single clock cycle, so there are no registers between the input and output of the function).

    One answer would be to break up the functions and pipeline them. You could then feed in the Timestamp to calculate minutes, then repeat after this completes to calculate minutes and so on. Store the results in registers, and when they're all complete send a ready signal back.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Someone mentioned that the integer variables I'm using dont have a specified range. So the max size I want them to be is 32 bits long. I set the range to be 0 to 4294967295 (2^32 -1) and I got an error

    --- Quote Start ---

    Error (10528): VHDL error at Main.vhd(196): value "0" is outside the target constraint range (0 to -1)

    --- Quote End ---

    Which makes sense because a value of xFFFFFFFF in a 32 reg signed would be -1. So I removed the initialization of the integers to 0 and everything compiled fine. Like someone mentioned the division was unknown width so the compiler was having trouble. Regardless its compiling fine now. Thanks to everyone!
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I think you may be misunderstand VHDL.

    Integers in VHDL are of the range -2^(31) to 2^31 - 1. So the numbers are always signed. You cannot have a range of 0 to 2^32-1 in VHDL. YOu have to use unsigned/signed types for numbers with larger ranges.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I declared them as type natural and I still get the same problem... 

    variable timestamp_int : natural range 0 to 4294967295 := 0;

    --- Quote Start ---

    Error (10528): VHDL error at Main.vhd(133): value "0" is outside the target constraint range (0 to -1)

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    natural is technically only 31 bits, because it is a subtype of integer. It has a range of 0 to 2^31 -1.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    What type can I use for a 32 bit unsigned value so that it would have a range from 0 to 2^32 - 1?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    the unsigned type from the numeric_std library

    variable n : unsigned(31 downto 0);
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I cant seem to use the unsinged type the way I would a natural or integer, it wont let me assign a value to it

    variable n : unsigned(31 downto 0) := 0;
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    To assign a constant value to an unsigned variable/signal, you have to use a constant with a length specification, a conversion function (e.g. conv_unsigned) or an expression like n:=(others => '0');

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I'm trying to pipeline the algorithm. I seperated the function so that there are very few operations in each stage. I essentially broke each function into a state machine where an operation is performed on each state. This still is too much for the synthesis and I dont know why? Shouldn't it only be using a single adder or multiplier in each state?