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Altera_Forum
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15 years ago

Conversion uses all combinational logic

Hi, I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm trying to pipeline the algorithm. I seperated the function so that there are very few operations in each stage. I essentially broke each function into a state machine where an operation is performed on each state. This still is too much for the synthesis and I dont know why? Shouldn't it only be using a single adder or multiplier in each state?