Forum Discussion
Altera_Forum
Honored Contributor
15 years agoConversion uses all combinational logic
Hi, I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip. ...
Altera_Forum
Honored Contributor
15 years agoIts the functions that add all of the dividers, that kill your FMAx down to 1.5MHz, because none of them are clocked (you are calculating all those values in a single clock cycle, so there are no registers between the input and output of the function).
One answer would be to break up the functions and pipeline them. You could then feed in the Timestamp to calculate minutes, then repeat after this completes to calculate minutes and so on. Store the results in registers, and when they're all complete send a ready signal back.