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Altera_Forum
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15 years ago

Conversion uses all combinational logic

Hi, I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Someone mentioned that the integer variables I'm using dont have a specified range. So the max size I want them to be is 32 bits long. I set the range to be 0 to 4294967295 (2^32 -1) and I got an error

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Error (10528): VHDL error at Main.vhd(196): value "0" is outside the target constraint range (0 to -1)

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Which makes sense because a value of xFFFFFFFF in a 32 reg signed would be -1. So I removed the initialization of the integers to 0 and everything compiled fine. Like someone mentioned the division was unknown width so the compiler was having trouble. Regardless its compiling fine now. Thanks to everyone!