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Altera_Forum
Honored Contributor
Honored ContributorConversion uses all combinational logic
Hi, I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip. ...
Altera_ForumHonored Contributor
Honored ContributorI think you may be misunderstand VHDL.
Integers in VHDL are of the range -2^(31) to 2^31 - 1. So the numbers are always signed. You cannot have a range of 0 to 2^32-1 in VHDL. YOu have to use unsigned/signed types for numbers with larger ranges.
