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Altera_Forum
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15 years ago

Conversion uses all combinational logic

Hi, I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I think you may be misunderstand VHDL.

Integers in VHDL are of the range -2^(31) to 2^31 - 1. So the numbers are always signed. You cannot have a range of 0 to 2^32-1 in VHDL. YOu have to use unsigned/signed types for numbers with larger ranges.