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Altera_Forum
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15 years ago

Conversion uses all combinational logic

Hi, I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I cant seem to use the unsinged type the way I would a natural or integer, it wont let me assign a value to it

variable n : unsigned(31 downto 0) := 0;