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Altera_Forum
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15 years ago

Conversion uses all combinational logic

Hi, I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I declared them as type natural and I still get the same problem... 

variable timestamp_int : natural range 0 to 4294967295 := 0;

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Error (10528): VHDL error at Main.vhd(133): value "0" is outside the target constraint range (0 to -1)

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