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Altera_Forum
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15 years ago

Conversion uses all combinational logic

Hi, I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

To assign a constant value to an unsigned variable/signal, you have to use a constant with a length specification, a conversion function (e.g. conv_unsigned) or an expression like n:=(others => '0');