Configuring Arria10 from HPS
Hello everyone,
I'm using the HAN Pilot Platform with the Arria 10AS066K3F40E2SG FPGA Chip.
Quartus Version 24.3
Embedded Shell Version 20.1
I want to configure the FPGA via HPS on a very basic level, like this https://github.com/zangman/de10-nano/blob/master/docs/Flash-FPGA-from-HPS-running-Linux.md .
Therefore i compiled the GHRD Project for the Platform and generated a bootloader and kernel accordingly to this guide from rocketboards (https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10).
U-boot branch: socfpga_v2024.04
Kernel branch: socfpga-6.6.22-lts
The rootfs is a debian bookworm which i generated by following information from this link (https://github.com/zangman/de10-nano/blob/master/docs/Debian-Root-File-System.md).
The bootlader, kernel and OS are working fine (at least from my perspective). No errors are shown in the logs during boot and basic operation of the OS.
Now if I want to configure the FGPA from the HPS I follow the information provided at the top of the post.
In my generated dtb (which I generated at the kernel generation step) a soc/base_fpga_region placeholder exists. And I generated a dtbo file to load the overlay.
The command (echo -n "blink.dtbo" > blink/path) for loading the device tree overlay fails in the shell with the following error message: "-bash echo: write error: Invalid argument"
If I look into the fpga_manager status i get: "write init error"
If i look at dmesg and get:
"fpga_manager fpga0: writing blink.rbf to SoCFPGA Arria10 FPGA Manager"
"fpga_manager fpga0: Error preparing FPGA for writing"
"fpga_region region0: failed to load fpga image"
"OF: overlay: overlay changeset per-apply notifier error -22, target /soc/base_fpga_region"
So far I checked everything for errors in compilation and logs. I also searched for other guides and ressources but could not find anything specific.
Unfortunately i cant find my errors, could you please help me solving this issue?
Thank you in advance for all replies
Hi,
I found the below link where it is mentioned that configuring the FPGA fabric from Linux using the Linux device tree overlays method is not supported in Intel® Arria® 10 SoC FPGA
https://www.intel.com/content/www/us/en/support/programmable/articles/000090173.html
But, you can use the partial reconfiguration (PR) solution where Linux device tree overlays method is supported.
Regards
Tiwari