Configuring Arria10 from HPS

Hi Tiwari,

thank you very much for your response.

I tried the partial reconfiguration solution you mentioned.

I kept my current Quartus and kernel versions and followed the guide from RocketBoards. Since I am using a more recent version of Quartus, some steps—such as selecting the synthesis mode for a revision—are no longer available in the Revisions window. Additionally, the Freeze Controller Intel FPGA IP is no longer listed in the IP Catalog, as it has been deprecated? Instead, I used the Partial Reconfiguration Controller Intel FPGA IP which contains the freeze controller. Based on the information from Intel's AN797 guide (https://cdrdv2-public.intel.com/666943/an797-683497-666943.pdf), I managed to create a design (base implementation and persona implementation) that compiled successfully without errors.

Unfortunately, the resources from the RocketBoards website—such as “linux-socfpga-pr-17.0-a10.tar.gz”—are no longer accessible, so I couldn’t check the DTBO files. I assume the RocketBoards guide is based on Intel’s AN798 guide (https://cdrdv2-public.intel.com/667007/an798-683034-667007.pdf), so I used the DTSO files provided there.

Unfortunately, I encountered the same error when trying to apply the device tree overlays for partial reconfiguration.

I am trying to use modern software versions because I want to maintain an up-to-date system for the partial reconfiguration approach.

Over the weekend, I will attempt to build a design using the older Quartus version and the previous kernel in order to get a working design.
I will update you on Monday.

Best regards,
Fox