Clock recovery from signle 125MHz pulses with PLL

yes. You'll see a window after you configure the FPGA saying you are in evaluation mode. Don't close this window and you can use the NCO. It will stop working when you close the window, or after a certain delay (1 hours IIRC) if you disconnect the USB blaster.

I opened megafunction wizard and found NCO. Are there any restrictions to using this megafunction ?

Hi,

The sophisticated functionality offered with the NCO core is the resource saving way to generate high resolution sine waves. A basic digital NCO as required for a ADPLL isn't more than a simple phase accumulator, involving a few lines of HDL code. The method is explained in the NCO user manual. Also low and medium resolution sine generators can be easily implemented without referring to the Altera core if you don't have a Quartus subscription license.

Yes you need to pay a license for it, or use it in evaluation mode (i.e. with the USB blaster connected all the time, and you can't flash your project)

Hi,

The core of an ADPLL would be a NCO generating the 176.4 kHz clock. Using a PI loop filter, it can ideally average the jitter of the sync signal to +/- 0.5 * 8ns, provided there's no additional jitter source than sampling the input signal at 125 MHz.

Hi,

process (clk_125_in, synchronized)
 begin
  if rising_edge(clk_125_in) then
        if synchronized = '1' then
        -- rest of the code - used as "rising edge" of the "recovered clock"

I mean if you generate clock at 41.2KHz as such from inversion then it is a clock that is generated by gating as opposed to PLL. There is nothing wrong with this generation but then I will avoid using it as clock for edge triggering those registers. This means I will use your system clock(125Mhz) to trigger edges and use sync itself as clock enable on those registers. So I don't need to convert sync to clock in the first place.