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Altera_Forum
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13 years ago

Clock recovery from signle 125MHz pulses with PLL

Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
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Altera_Forum
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13 years ago

yes. You'll see a window after you configure the FPGA saying you are in evaluation mode. Don't close this window and you can use the NCO. It will stop working when you close the window, or after a certain delay (1 hours IIRC) if you disconnect the USB blaster.